1. Field of the Invention
The present invention relates to a semiconductor memory device and particularly, to addressing in a case where a memory and a logic circuit are integrally formed on one chip.
2. Description of the Background Art
In design of an embedded dynamic random access memory that is constructed of a memory and a logic circuit driving the memory on one chip, a designer keeps on hand memory macros ready to use in which the number of bits in an array and the number of banks can be varied, in order to response to many requirements.
Description will be given of a conventional embedded memory macro using FIG. 21. A memory macro shown in FIG. 21 has a 4-bank configuration each bank of which has a memory capacity of 8 Mbits and realizes a total memory capacity of 32 Mbits. A bank B0 is constructed of blocks B0a and B0b disposed on both sides of a central control band 900. Likewise, banks B1, B2 and B3 are constructed of pairs of blocks, B1a and B1b; B2a and B2b; and B3a and B3b, respectively disposed both sides of the central control band 900. Each bank includes a plurality of memory cells M disposed in a matrix arrangement; a plurality of word lines (WL) disposed in correspondence to a plurality of rows and a plurality of bit lines (BL) disposed in correspondence to a plurality of columns. It should be appreciated that, in an example shown in FIG. 21, each block has 512 word lines.
In the central control band 900, a signal line 902 is disposed for transmission of an address. The signal line 902 transmits a signal output from an address buffer 904. A row decoder 906 performs row selection according to an output of the signal line 902.
The banks B0, B1, B2 and B3 are configured such that four 2-Mbit memory blocks are stacked. A memory capacity can be adjusted in memory blocks of 2 Mbits as a unit.
Further, the bank configuration is not limited to the 4-bank configuration but there can also be adopted a 2-bank configuration in which the entire memory blocks are grouped into two banks or a 1-bank configuration in which the entire memory blocks are used as one bank.
In each memory block, a redundant word line is disposed. Any defective word line can be replaced with a redundant word line not only in a memory block in which the redundant word line is disposed, but also in any of 4 memory blocks in the same bank in which the redundant word line is disposed.
In this configuration, a row address specifying a row direction, input externally, is latched at an address buffer 904 and sent to the signal line 902 disposed in the central control band 900 at a proper timing. At this time, part of the row address is predecoded. The row address 906 is sent from the signal line 902 running through the central control band 900. A signal received from the signal line 902 is decoded by the row decoder 906.
A word line WL is activated by the row decoder 906. Furthermore, a memory cell M is selected according to a column address, input externally. When a read operation is specified by the logic circuit, a data on a selected memory cell is output to the logic circuit. When a write operation is specified by the logic circuit, a data received from the logic circuit side is written onto a selected memory cell.
Description will be given of an address map for a row address in a memory macro with such a configuration. In the figure, RA0 to RA12 indicates respective row address signals, and BA0 to BA1 indicates respective bank address signals. A mark xe2x80x9c/xe2x80x9d means inversion. For example, when /RA12 is at H level if the row address signal RA12 is at L level. Further, m0 to m15 indicates memory blocks.
Referring to FIG. 22, in a 1-bank configuration, the row address signals RA9 to RA12 are used in order to specify a memory block. The memory block m0 is selected by activating the row address signals /RA12, /RA11, /RA10 and /RA9; the memory block m1 is selected by activating the row address signals /RA12, /RA11, /RA10 and RA9; the memory block m2 is selected by activating the row address signals /RA12, /RA11, RA10 and /RA9; and the memory block m3 is selected by activating the row address signals /RA12, /RA11, RA10 and RA9.
The memory block m4 is selected by activating the row address signals /RA12, RA11, /RA10 and /RA9; the memory block m5 is selected by activating the row address signals /RA12, RA11, /RA10 and RA9; the memory block m6 is selected by activating the row address signals /RA12, RA11, RA10 and /RA9; and the memory block m7 is selected by activating the row address signals /RA12, RA11, RA10 and RA9.
The memory block m8 is selected by activating the row address signals RA12, /RA11, /RA10 and /RA9; the memory block m9 is selected by activating the row address signals RA12, /RA11, /RA10 and RA9; the memory block m10 is selected by activating the row address signals RA12, /RA11, RA10 and /RA9; and the memory block m11 is selected by activating the row address signals RA12, /RA11, RA10 and RA9.
The memory block m12 is selected by activating the row address signals RA12, RA11, /RA10 and /RA9; the memory block m13 is selected by activating the row address signals RA12, RA11, /RA10 and RA9; the memory block m14 is selected by activating the row address signals RA12, RA11, RA10 and /RA9; and the memory block m15 is selected by activating the row address signals RA12, RA11, RA10 and RA9.
Referring to FIG. 23, in a 2-bank configuration, a bank address signal BA0 is assigned onto a signal line on which the row address signal RA12 has been assigned in the 1-bank configuration, and the bank address signal BA0 is used for switching-over between banks.
Referring to FIG. 24, in a 4-bank configuration, bank address signals BA0 and BA1 are assigned onto respective signal lines on which the row address signals RA11 and RA12 have been assigned in the 1-bank configuration, and the bank address signals BA0 and BA1 are used for switching-over between banks.
The row address signals RA0 to RA8 are used to specify word lines in a memory block regardless of a bank configuration.
In a case where a memory capacity of a memory macro in such a conventional memory chip is changed, a layout of a memory cell array is changed as shown in FIGS. 25 to 27. FIG. 25 corresponds to a 1-bank configuration, FIG. 26 corresponds to a 2-bank configuration; and FIG. 27 corresponds to a 4-bank configuration. In any case of the bank configurations, a memory capacity is of 24 Mbits. Portions shaded by hatching in the figure indicate regions where no layout configuration is present in a 24-Mbit configuration.
Referring to FIG. 25, in a case of the 1-bank configuration, a portion other than addresses xe2x80x9c1800xe2x80x9d to xe2x80x9c1FFFxe2x80x9d in hexadecimal notation (the hexadecimal notation is hereinafter applied) of row addresses xe2x80x9c0000xe2x80x9d to xe2x80x9c1FFFxe2x80x9d are an address space.
Referring to FIG. 26, in a case of the 2-bank configuration, portions other than addresses xe2x80x9cF00xe2x80x9d to xe2x80x9cFFFxe2x80x9d of row addresses xe2x80x9c000xe2x80x9d to xe2x80x9cFFFxe2x80x9d are address spaces.
Referring to FIG. 27, in a case of the 4-bank configuration, portions other than addresses xe2x80x9c600xe2x80x9d to xe2x80x9c7FFxe2x80x9d of row addresses xe2x80x9c000xe2x80x9d to xe2x80x9c7FFxe2x80x9d are address spaces.
In such a manner, in a case where the 1-bank configuration is realized with a memory capacity of 24 Mbits, 8 Mbits in an edge portion of a memory cell array of 32 M bits are removed from the memory cell array of 32 Mbits. Further, in a case where the 2-bank configuration is realized with a memory capacity of 24 Mbits, a total of 8 Mbits in central and edge portions of a memory cell array is removed from the memory cell array of 32 Mbits. Still further, in a case where the 4-bank configuration is realized with a memory capacity of 24 Mbits, 2 Mbits in each of 4 regions of a memory cell array of 32 Mbits, obtained by dividing the memory cell array are removed from the memory cell array.
While a region or regions which are removed in a memory cell array are in position different according to a bank configuration, this is because consecutive addresses in a bank is realized.
In such a conventional memory chip, there has arisen a problem described below in a case where different banks with the same layout as each other or one another are realized. For example, when address spaces of 2 banks are assigned in a layout of 1-bank configuration, as shown in FIG. 28; an address space of a bank B0 includes xe2x80x9c000xe2x80x9d to xe2x80x9cFFFxe2x80x9d and an address space of a bank B1 includes xe2x80x9c000xe2x80x9d to xe2x80x9cEFF.xe2x80x9d Therefore, A memory space of 16 Mbits is assigned to the bank B0 and a memory space of 8 Mbits is assigned to the bank B1. That is, amounts of memory assignment to the respective banks are different from each other.
When an address space of the 1-bank configuration is assigned to a layout of 4-bank configuration, as shown in FIG. 29; an address space of the bank B0 includes xe2x80x9c0000xe2x80x9d to xe2x80x9c05FF,xe2x80x9d xe2x80x9c0800xe2x80x9d to xe2x80x9c0DFF,xe2x80x9d xe2x80x9c1000xe2x80x9d to xe2x80x9c15FF,xe2x80x9d and xe2x80x9c1800xe2x80x9d to xe2x80x9c1DFF.xe2x80x9d That is, parts of the address spaces are lost. Therefore, the address spaces become inconsecutive and fall into a state difficult to use for a user.
In this way, 1-, 2- and 4-bank configurations can be realized by replacing some of row addresses in a case of a memory capacity of 32 Mbits. Therefore, only one kind of a layout for a memory array is sufficient and different bank configurations can be realized with the same mask. However, if a memory cell array with different bank configurations is sought to be realized with the same mask while changing a memory capacity, an imbalance occurs in a memory space of each bank or inconsecutiveness arises in an address space.
Therefore, in a conventional practice, a different layout (different mask) has been necessary for each bank configuration as shown in FIGS. 25 to 27.
The present invention provides a semiconductor memory device being capable of realizing a consecutive memory space even when a bank configuration is altered, with the same mask.
A semiconductor memory device according to an aspect of the present invention includes: a memory macro including: a memory cell array region having a plurality of memory cells disposed in a matrix arrangement, a plurality of word lines disposed in correspondence to a plurality of rows, and a plurality of bit lines disposed in correspondence to a plurality of columns; and a select circuit for selecting a memory cell, a layout of the memory macro being determined according to a memory capacity; a logic circuit specifying operation of the memory macro; and an address connection line for transmitting an address to select a memory cell to the memory macro from the logic circuit, disposed between the logic circuit and the memory macro, wherein the address connection line is interconnected according to a bank configuration of the memory cell array region such that consecutiveness of an address space in a bank is maintained.
It is preferable that the plurality of memory cells are grouped into a plurality of memory blocks, the address include: a word line select address; and a block select address having a plurality of bits, the select circuit selects not only a memory block according to a block select address but also a specific word line included in the selected memory block according to a word line select address, and the address connection line is interconnected such that higher order bits of a block select address output from the logic circuit are assigned to lower order bits of the block select address in the memory macro, while lower order bits of the block select address output from the logic circuit are assigned to higher order bits of the block select address in the memory macro.
It is more preferable that the higher order bits of the block select address output from the logic circuit includes a bank address specifying a bank to be selected among a plurality of banks and the address connection line is interconnected such that in the memory macro, a bank address is assigned to the higher order bits of the block select address.
Particularly, each of the plurality of banks further includes a spare word line for substituting for a defective word line and the defective word line is replaced with the spare word line in a bank where the defective word line is present.
It is more preferable that the higher order bits of the block select address output from the logic circuit includes a bank address specifying a bank to be selected among a plurality of banks and the address connection line is interconnected such that in the memory macro, a bank address is assigned to the lower order bits of the block select address.
Particularly, each of the plurality of memory blocks further includes a spare word line for substituting for a defective word line and the defective word line is replaced with the spare word line in a memory block where the defective word line is present.
According to the semiconductor memory device relating to the present invention, consecutive memory spaces can be realized even in a case where different banks are realized with the same mask.
Hence, a mask is not necessary to make for each bank configuration. Further, since consecutive memory spaces can be realized, there is provided an environment that a user is easy to use.
Further, when the higher order bits and lower order bits of a block select address except a bank address are interchanged therebetween, a normal replacement operation is ensured in the memory macro having a redundancy configuration in which, in the same bank, a defective word line is replaced with a spare word line.
Further, when the higher order bits and lower order bits of a block select address except a bank address are interchanged therebetween, a normal replacement operation is ensured in a memory macro having a redundancy configuration in which, in the same memory block, a defective word line is replaced with a spare word line.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.